VDC
Testing.... WIP HuC6270 - Video Display Controller (VDC) AKA "7UP" 16-bit monolithic CMOS video display controller IC with an externally synchronizable sync signal generator and external Video RAM (VRAM). Screen layers: 1 background + sprites (sprites can be in front or behind BG) Background character sizes: 8×8 dot Number of background characters in CG: 4096 Sprite sizes: 16×16, 16×32, 16×64, 32×16, 32×32, 32×64 dot Number of on-screen sprites: 64 Number of sprites per scanline: 16 (256 sprite pixels) Number of sprites in SG: 1024 (if 64 kB words in VRAM is used) VRAM: 64 kB Power supply: 5 V Package: 80-pin plastic flat package Note: The SuperGrafx has two HuC6270 chips which makes it possible for 2 background layers, 128 sprites on-screen, and 128 kB VRAM. Each background layer allows 16 sprites per scanline so the total is 32 sprites or 512 sprite pixels per scanline on the SuperGrafx. Port registers The internal registers in the VDC are accessed using the port registers. VDC_SR ($0000) (W) Address Register Returns internal status of the VDC. Reading also acknowledges interrupts. FEDCBA98 76543210 ||||||+- CR Collision detection - Set if: Sprite #0 has collided |||||| with sprite #1~#63. |||||+-- OR Over detection - Set if: ||||| 1) More than 17 sprites on a scanline. ||||| 2) Sprite pattern data can not be fetched during hblank. ||||| 3) All sprite pattern data can not be fetched into the ||||| shift register because the CGX is set in the SAT (Sprite ||||| Attribute Table) for some of the sprites. ||||+--- RR Raster detection - Set if: The scanline (rasterline) |||| counter has reached the scanline set in the scanline ||| detection register. |||+---- DS DMA (VRAM-SATB) End Detection - Set if: ||| Data block transfer between VRAM and SATB is complete. ||+----- DV DMA (VRAM-VRAM) End Detection - Set if: || Data block transfer between two VRAM areas is complete. || If a vertical display period starts, the DMA will be || aborted, and in this case no end detection will occur. |+------ VD Vertical Blanking Detection - Set if: The vblank | period has started. +------- BSY Busy - This indicates that the CPU is reading or writing to VRAM. Even if BSY is set, no interrupt (IRQ) will occur. If BSY is set, do not write data to IW (bits 11 and 12 of R05). Basically provides BUSY pin information, but with reversed logic. VDC_DATA_L ($0002) (R/W) VDC_DATA_H ($0003) (R/W) Data Registers After selecting VDC register via AR, read or write the data via these two registers. Only immediate addressing allowed. The ST1 and ST2 instructions of the HuC6280 can be used to quickly write immediate values to these two registers respectively. Ex: Write $00C0 to CR to enable background and sprites: st0 #$05 ;select CR (R05) st1 #$C0 ;write $C0 to the low byte of CR st2 #$00 ;write $00 to the high byte of CR Note that only immediate values may be written. Other values must be written using the accumulator (or X/Y index registers) like normal. Internal registers: registers here